The present disclosure relates to a phase locked loop (PLL) including a plurality feedback loops coupled together.
PLLs including a feedback loop having an oscillator for outputting an oscillating signal according to an input, and a phase comparator for obtaining a phase difference (phase deviation) between the oscillating signal and an input signal and outputting a signal corresponding to the phase deviation to the oscillator have been known. Such a PLL is configured, for example, as shown in FIG. 8, such that an input signal to a circuit 101 and an oscillating signal output from an oscillator 102 (an output signal from a frequency divider 105 in an example shown in FIG. 8) are compared by a phase comparator 103 to output a signal corresponding to the comparison result to the oscillator 102. Thus, a PLL allowing synchronization of the phase of the signal output from the oscillator 102 with the phase of the input signal can be obtained. In FIG. 8, the reference character 104 denotes a loop filter.
In a PLL having the above-described configuration, when the frequency of an input signal to the PLL is constant, a difference between the phases of the input signal and a signal output from the oscillator 102 can be substantially eliminated. However, when the frequency of an input signal varies, a difference between the phases of the input signal and the signal output from the oscillator 102 cannot be reduced to zero. Also, in the PLL, pull-in fluctuation, which is caused when an input phase in the phase comparator is pulled in or out in the course of pulling the frequency of an output signal into the frequency of the input signal from a non-synchronized state.
Thus, in order to deal with the above-described pull-in fluctuation caused when the frequency of an input signal varies, a so-called dual loop PLL in which two of the above-described PLLs are combined has been proposed. Such a dual loop PLL is described in, for example, Japanese Patent Application No. 2008-147788, and is also shown in FIG. 9. In the dual loop PLL, since one PLL is a feedforward element of the other PLL, fast tracking can be achieved, so that a period in which the pull-in fluctuation occurs can be reduced. Furthermore, with the frequencies of an input signal and an output signal synchronized, the phase deviation is kept close to zero even when the frequency of the input signal increases or decreases. Therefore, the phases of inputs to the phase comparator hardly become out of a range in which the phase comparator can perform phase comparison, and the pull-in fluctuation hardly occurs.
Specifically, in an example dual loop PLL 110 of FIG. 9, an adder 126 adds a signal output from a phase comparator 112 of a first PLL 111 to a signal output from a phase comparator 122 of a second PLL 121 and smoothed by a loop filter 125. A resultant value is input to an oscillator 123 of the second PLL 121. By configuring the dual loop PLL 110 to have the above-described configuration, a phase deviation obtained by the phase comparator 112 of first PLL 111 can be reflected to an input to the oscillator 123 of the second PLL 121. Thus, a good responsivity to variation in the frequency of the input signal can be provided, and the phase deviation can be reduced to be close to zero with high accuracy. In FIG. 9, the reference characters 113, 114 and 124 denote an oscillator of the first PLL 111, a frequency divider of the first PLL 111, and a frequency divider of the second PLL 121, respectively.
The above-described the dual loop PLL configuration is used in communication devices and broadcast receivers for receiving a signal transmitted from a high speed moving body such as an artificial satellite and the like for the purpose of eliminating steady-state errors caused by Doppler shift (frequency shift). In contrast to such use, the present inventor has conceived of use of a dual loop PLL in drive control of a motor or the like which is accelerated or decelerated, instead of such communication devices.
However, characteristics of motors are greatly different from those of communication devices, and therefore, if the known example configuration of the dual loop PLL described above is applied to drive control of a motor, drive control of the motor itself is difficult. Specifically, as shown in FIGS. 3A and 3B, although the oscillator of the PLL is configured to output a positive output signal even when the polarity of an input value (input voltage) is changed (see FIG. 3A), but the rotation direction of the motor is changed depending on the polarity of an input value (input voltage) in the motor (see FIG. 3B). Thus, when the oscillator 123 of the second PLL 121 of FIG. 9 is merely replaced with a motor including an encoder, the rotation direction of the motor is changed according to the polarity of an input value, so that drive control of the motor is impossible. Therefore, the application of the above-described configuration of the dual loop PLL to drive control of a motor is theoretically difficult.
Based on the foregoing, the PLL of FIG. 8 is applicable to drive control of a motor only when the frequency of an input signal is constant for the reason that the phase deviation with respect to variation in the frequency of the input signal cannot be reduced to zero, the pull-in fluctuation occurs, and the like. Also, because of the above-described characteristics of motors, the dual loop PLL of FIG. 9 cannot be applied to drive control of a motor.